1. Field of the Invention
The present invention relates to an offset voltage cancellation circuit for removing an offset voltage included in a differential signal that is output, using radio communication, by the detection circuit of a reception apparatus.
This application is counterparts of Japanese patent applications, Serial Number 182527/2002, filed June 24, the subject matter of which is incorporated herein by reference.
2. Related Arts
FIG. 2 is a diagram showing an example configuration for a conventional offset voltage cancellation circuit.
An offset cancellation circuit 90 comprises peak detectors 91 and 92 for respectively detecting, in differential input signals VA1 and VA2 received from a detection circuit 1, peak voltages VP1 and VP2; and resistors 93 and 94 for outputting, as a reference voltage VREF, an intermediate potential between the differential input signals VA1 and VA2.
The peak detectors 91 and 92, which are constituted by a voltage follower and a voltage retention capacitor, can immediately detect and cope with a rise in an input voltage and can store the maximum voltage attained. Then, when thereafter the input voltage is reduced, in congruity with a large time constant, the peak detectors 91 and 92 gradually discharge down the voltages they have stored to insure the performance of a stable operation.
The offset voltage cancellation circuit 90 also comprises: an adder 95 for adding the differential input signal VA1 to the peak voltage VP2,.while using as a reference the reference voltage VREF, and outputting a differential output signal VC1; and an adder 96 for adding the differential input signal VA2 to the peak voltage VP1, while using as a reference the reference voltage VREF, and outputting a differential output signal VC2.
Assume that the differential input signals VA1 and VA2, represented by equation (1), are provided for the offset voltage cancellation circuit 90.
VA1=VO1+A sin(xcfx89t)
VA2=VO2xe2x88x92A sin(xcfx89t)xe2x80x83xe2x80x83. . . (1)
It should be noted that VO1 and VO2 denote the direct-current voltages elements of the differential input signals VA1 and VA2, and A denotes the amplitude for the alternating-current elements of the differential input signals VA1 and VA2.
Then, the peak voltages VP1 and VP2 output from the peak detectors 91 and 92 and the reference voltage VREF generated by the resistors 93 and 94 are represented in equation (2) as follows.
VP1=VO1+A
VP2=VO2+A
xe2x80x83VREF=(VO1+VO2)/2xe2x80x83xe2x80x83. . . (2)
The differential input signal VA1, the peak voltage VP2 and the reference voltage VREF are transmitted to the adder 95 and the differential input signal VA2, the peak voltage VP1 and the reference voltage VREF are transmitted to the adder 96, and the respective signals and data are added together at the adders 95 and 96.
As a result, the respective differential output signals VC1 and VC2 output by the adders 95 and 96 are represented by equation (3) as follows.
VC1=VA1+VP2xe2x88x92VREF=A sin (xcfx89t)+A+(VO1+VO2)/2
VC2=VA2+VP1xe2x88x92VREF=xe2x88x92A sin (xcfx89t)+A+(VO1+VO2)/2xe2x80x83xe2x80x83. . . (3)
As is shown in equation (3), the differential output signals VC1 and VC2 have the same number of constant terms. This means that the direct-current voltage elements included in the differential output signals VC1 and VC2 are equal, and that the offset voltage is removed.
However, with the conventional offset voltage cancellation circuit the following problem is encountered.
The time-sharing communication for alternately changing the transmission state and the reception state is frequently employed for a radio communication system. As a time elapses, the signal received by this system is changed to a silent signal that includes only a noise element, a non-modulated carrier wave signal, a preamble signal or a modulated carrier wave signal. The direct-current voltage elements, which are included in the differential input signals VA1 and VA2 received from the detection circuit 1, differ, depending on the operating condition, and an offset voltage is generated in accordance with the direct-current voltage element.
In the offset voltage cancellation circuit in FIG. 2, the peak voltages 91 and 92 detect the peak voltages VP1 and VP2 of the differential input signals VA1 and VA2, and these peak voltages VP1 and VP2 are stored in capacitors (not shown). The voltages stored in the capacitors can immediately catch up with a rise in the peak voltages; however, when the peak voltages are reduced, the voltages stored in the capacitors are changed, in congruity with a large time constant, in order to ensure a stable operation is performed.
Therefore, when the potentials of the differential input signals VA1 and VA2 are temporarily increased due to a state change or a momentary noise, the retained peak voltages VP1 and VP2 are replaced by potentials having abnormal values, so that there are differences between them and the actual peak voltages. Thus, the peak voltages VP1 and VP2 retained by the peak detectors 91 and 92 do not match the values represented by equation (2), and the resulting offset between the differential output signals VC1 and VC2 prevents data from being received correctly.
To resolve the problem presented by the conventional technique, it is one objective of the present invention to provide an offset voltage cancellation circuit that can quickly cope with a state change, and can cancel an offset voltage between differential input signals.
To achieve this objective, according to a first aspect of the present invention, an offset voltage cancellation circuit, which removes a difference between direct-current voltage element included in first and second differential input signals, and generates a differential signal including first and second output signals, comprises: first and second peak detectors; first and second adders; and a peak level reset unit, all of which are described below.
The first peak detector includes a first capacitor for storing the peak level of the first input signal. The first peak detector outputs voltage corresponding to a charge stored in the first capacitor as a first peak voltage. The first peak detector also discharges a charge stored in the first capacitor in response to a reset signal. The second peak detector includes a second capacitor for storing the peak level of the second input signal. The second peak detector outputs a voltage corresponding to a charge stored in the second capacitor as a second peak voltage, and discharges a charge stored in the second capacitor in response to the reset signal.
The first adder adds the first input signal to the second peak voltage to generate the first output signal, and the second adder adds the second input signal to the first peak voltage to generate the second output signal. The peak level reset unit outputs the reset signal corresponding to a potential difference between the first and second output signals.
According to a second aspect, an offset voltage cancellation circuit comprises: the first and second peak detectors and the first and the second adders, which are the same as those in the first aspect; a reset controller which monitors the peak voltages of the first and second output signals and which outputs a reset enable signal when a difference between said peak voltages exceeds a predetermined level a reset controller; and a peak level reset unit which outputs the reset signal corresponding to a potential difference between the first and the second output signals when the reset enable signal is received thereto.
According to a third aspect of the present invention, an offset voltage cancellation circuit comprises: the first and second peak detectors and the first and second adders, which are the same as those for the first aspect; and a peak level reset unit which outputs the reset signal corresponding to a potential difference between the first and the second output signals when a difference between the peak voltages of the first and the second output signals exceeds a predetermined level.
According to the present invention, the following operations are performed by the thus arranged offset voltage cancellation circuit.
The peak voltages of the first and the second input signals are respectively detected by the first and the second peak detectors, and are stored in the first and the second capacitors. Further, the first input signal is added to the second peak voltage by the first adder, and the first output signal is generated. The second input signal is then added to the first peak voltage by the second adder, and the second output signal is generated. So long as the levels of the input signals are stabilized, through the addition performed by the first and second adders, the value of the direct-current voltage element included in the first output signal corresponds to the value of the second output signal and the offset voltage is canceled.
When the level of the input signal is changed and the peak voltage held by the first or second peak detector is raised, the level of the first or the second output signal is changed, and the potential difference between these output signals is increased. Therefore, the level of the reset signal output by the peak level resetting signal is increased, the capacitors of the first and second peak detectors are discharged, and the first and second peak voltages are reset. Then, the first and second peak voltages are maintained in accordance with the first and second signals that are newly input.